The present invention relates in general to the field of verification of electronic circuit designs, and in particular to a method to verify an electronic circuit design and a circuit arrangement to verify an electronic circuit design. Still more particularly, the present invention relates to a data processing program and a computer program product to verify an electronic circuit.
In the verification of complex chip logic designs today verification engineers waive a large number of defects that they deem tolerable to leave unfixed for various reasons. Responsibility for granting waivers is distributed across teams and so is the information regarding which waivers have been granted. Moreover, many waivers have an expiration date by which the defect is expected to be fixed, e.g., after a particular chip release. Finally, waivers are typically documented in a defect tracking system in an unstructured format, giving the type of defect, the exact affected component on the chip and the person granting the waiver in plain English. Some known tracking systems offer a coarse possibility to name sub-systems of the chip in which a found defect is located.
Automatic determination of whether hardware design defects should be waived using a hardware design verification tool, e.g. design rule checker (DRC), electrical rule checker (ERC), structural verification tool, etc. in order to suppress error messages is not currently possible. A waiver is comprised of a hardware component identifier, e.g. a name and an associated defect type, preferably with a hierarchy information, e.g. an hierarchical name <Top Level Name>.<Level2 Name> . . . <Bottom Level Name> as a hierarchical waiver. For example, a waiver list can be implemented as a file with each line containing the defect type and the hierarchical signal name. Another example is to use multiple files, wherein a file is associated to a defect type and contains only the hierarchical signal names per line.
In the Patent Application Publication US 2005/0188336 A1 “SYSTEM AND METHOD FOR WAIVING A VERIFICATION CHECK” by Mortensen et al. a system and method for waiving verification check associated with a circuit design is disclosed. According to the disclosed system and method a first engine integrates waiver options associated with the circuit design's objects into a hierarchical verification tree having the verification check. A second engine traverses a portion of the hierarchical verification tree to determine a list of applicable waivers. A third engine resolves the list of applicable waivers to determine the disposition of the verification check violation. The third engine combines multiple hierarchical waivers to determine if a defect is waived or not, and needs to query a database for each defect found by the verification separately. The used waivers are defined by a hardware component identifier and an associated defect type only.